The present invention relates to a semiconductor device and its manufacturing technology, for example, a semiconductor device having a rewiring (redistribution layer) and a technology effective when it is applied to the manufacturing technology of the semiconductor device.
Japanese Unexamined Patent Application Publication No. 2014-22505 (Patent Document 1) describes a structure in which a rewiring is comprised of a copper film (Cu film), a nickel film (Ni film), and a palladium film (Pd film) successively stacked from the side of a semiconductor substrate and a copper wire is coupled to the upper surface of the palladium film.
Japanese Patent No. 5412552 (Patent Document 2) describes that a predetermined or more occupancy of a rewiring is required for stable formation of a copper film by plating.
Japanese Patent No. 5132162 (Patent Document 3) describes arrangement of a dummy pattern at the side of a fuse wiring as an arrangement example of a dummy pattern around a wiring.
Japanese Unexamined Patent Application Publication No. 2012-253071 (Patent Document 4) describes a technology of placing a dummy pattern comprised of a dot pattern around a wiring layer.
Japanese Unexamined Patent Application Publication No. Hei 5(1993)-258017 (Patent Document 5) describes a technology of arranging dummy patterns in mesh form at the entire periphery except wirings.